Memory technology has progressed considerably in recent years. Since the operational speed and the manipulation data amount of a central processing unit (CPU) is increasing, the performance of a memory cell is increasing at the same time. For example, high speed erasing is a popular method for improving the performance of a memory. Volatile storage memories such as random access memory (RAM) is widely used in computer nowadays. But the stored data vanishes due to the power break off. Another nonvolatile storage memories such as mask read only memory (Mask ROM), erasable programmable ROM (EPROM), or electrically erasable programmable ROM (EEPROM) will not lost the stored messages when lack of power and will be better for some specific usage.
Flash memories are also a nonvolatile storage memory with similar structure as EEPROMs. They have a very high speed erasing feature in either an overall region or a local region thereof, therefore they are very popular in the computer field also. For example, they are used to replace the read-only memories to store the firmware such as BIOS (basic input/output system). The users can easily update their BIOS by rewriting the flash memory.
Conventional flash memory cells have a double or triple layer of polysilicon structure. The upper most polysilicon layer is patterned to form the control gates and the word lines of the structure, and the second polysilicon layer is patterned to form the floating gates as a double layer structure. A third polysilicon layer is patterned as select gates to form the triple layer polysilicon structure. No matter what the structures of the flash memories are, the characteristic of tunnel oxide layer between the substrate and the floating gate is a key factor for the operation of flash memories.
Although the scale down of devices is the trend for semiconductor fabrication, the flash memories cannot scale down the thickness of tunnel oxide in order to avoid leakage current problem. For example, the thickness of tunnel oxide between about 90 to 100 angstroms will be used in 1.0 .mu.m generation as well as 0.25 .mu.m generation.
Alternatively, there are configurations of single-poly flash memories together with logic circuitry. When embedding memory cells into a standard logic process, it is desirable to do so without changing the single-poly process typically used in the fabrication of the logic circuitry. This desire has led to the development of a single-poly flash memory cell having the same N+ source and drain regions formed in a P type substrate. An N diffusion region formed in the P type substrate serves as the control gate and is capacitively coupled to the floating gate via a thin oxide layer. That is, tunnel oxide layer. Since the control gate and floating gate of this singly-poly flash cell form a capacitor in a manner similar to that of the more traditional stacked-gate, double-poly, or triple-poly flash cells, the single-poly flash cell is programmed, erased, and read in a manner similar to that of the conventional flash cell.
Furthermore, when we fabricate the semiconductor devices above 0.5 .mu.m generation, the thickness of gate oxide layer of the logic cell is thicker than tunnel oxide layer of embedded flash cell. Accordingly, the tunnel oxide layer of embedded flash cell can be grown last together with the gate oxide layer of the logic cell. A high quality tunnel oxide layer can be achieved easily due to one step processing. Nevertheless, when the periphery logic cell is scale down due to cost saving and lower power consumption, the thickness of gate oxide layer can be formed from, for example, about 130 A at 0.5 .mu.m generation and reduced to about 70 A at 0.35 .mu.m generation. The typical thickness of the logic gate oxide layer at 0.35 .mu.m generation is thinner than the normal tunnel oxide layer thickness (between about 90.about.100 angstroms) and the tunnel oxide last grown would not work. Prior art techniques introduce composite tunnel oxide to solve this problem but it will degrade the quality and cycling performance of tunnel oxide. Another approach is to compromise the periphery circuit performance and use the thicker gate oxide. (e.g. 95 A) To compromise between the logic cell and the flash cell, the standard logic cell library cannot be implemented since it is not a truly embedded flash cell.